Digital video signal processing circuitry generally samples a video signal in response to a clock signal which is synchronized to one synchronization component of the video signal. For example, in a standard NTSC video signal, the video signal may be sampled by a clock synchronized to the color burst signal and having a frequency of four times the color burst signal frequency (termed a burst-locked clock). In a standard NTSC video signal, such a sample clock signal has 910 pulses in one horizontal line. While the phase of such a sample clock signal is independent of the phase of the line (e.g. horizontal) synchronization component, the phase difference between them remains constant.
However, digital video signal processing circuits often must process non-standard video signal. In these signals, the phase difference between the burst locked clock and the line synchronization component varies from line to line. This situation can occur in video cassette recorders and/or video disc players in which the recording medium is affected with mechanical jitter on playback. The effects are exacerbated in processing circuits which store frames of digital video data for functions such as noise reduction and frame comb luminance/chrominance component separation, and features such as freeze frame and picture-in-picture.
To perform such functions, and provide such features, it is required to process samples from spatially aligned raster locations in adjacent frames. That is, the two samples must be from the same line in each frame, and have the same time delay from the horizontal synchronization signal in that line. However, because of the phase changes between the burst locked sample clock and the horizontal synchronization signal from line to line and frame to frame, as described above, a sample in a line of one frame will not necessarily be spatially aligned with a sample in the same line in the previous frame.
It is known to calculate the phase difference (termed skew) between the burst clock signal and the horizontal synchronization signal in each line. (See U.S. Pat. No. 5,309,111, "Apparatus for Measuring Skew Timing Errors," issued May 3, 1994 to McNeely et al., incorporated by reference.) It is also known to interpolate between two samples in a line of one frame to generate an interpolated sample which is spatially aligned (i.e. at the same delay from the horizontal synchronization signal) with a sample in that same line of the previous frame, using the difference in skew between the two lines as the interpolation parameter. This interpolated sample is then processed, along with the sample from the previous frame, to provide the functions and features described above. (See U.S. Pat. No. 4,667,240, "Timing Correction Circuitry as for TV Signal Recursive Filters," issued May 19, 1987 to Willis et al., incorporated by reference.) It is also known to store only visible samples (i.e. non-blank samples) in the frame store to minimize the required capacity of the frame store. Thus, in such systems, the taking and storing of video samples is delayed from the horizontal synchronization signal by a period substantially equal to the horizontal blanking interval.
Such systems use a logic gate, or flip-flop, responsive to the horizontal synchronization signal, and clocked by the burst locked clock, to detect the horizontal synchronization signal. FIGS. 1, 2 and 3 are waveform diagrams illustrating how an uncertainty condition can arise in such systems. In FIG. 1, the topmost waveform, CLOCK, illustrates the burst locked clock near the start of a horizontal line. The second waveform, H SYNC, illustrates the horizontal synchronization signal for the horizontal line. As can be seen, the leading edge 201 (negative going) of the horizontal synchronization signal occurs nearly at the middle (i.e. near the negative going transition) of cycle 0 of the burst locked clock, CLOCK. The third waveform, SYNC DETECTED, represents the output of the horizontal synchronization signal detector, which may, for example, be a flip-flop. The SYNC DETECTED signal goes high 202 at the leading edge of cycle 1 of the burst locked clock, CLOCK, after the leading edge 201 of the horizontal synchronization signal H SYNC. The fourth waveform, SAMPLE, illustrates the sample clock. The sample clock begins on the fourth cycle of the burst locked clock CLOCK after the horizontal synchronization signal H SYNC was detected 202, which in the illustrated embodiment is assumed to be the beginning of the visible samples. In an actual embodiment, the number of burst locked clock cycles from the detection of the horizontal synchronization signal to the first visible video sample may be different. One skilled in the art will understand how to adjust the delay appropriately.
Logic circuits such as the flip-flop forming the horizontal synchronization signal detector, generally are guaranteed to operate properly only if the signal being sampled (in this case, the horizontal synchronization signal) is stable from a predetermined time before a transition of the clock signal (in this case, the burst locked clock signal) called the set-up time, through a predetermined time after the transition of the clock signal called the hold-time. Otherwise, the operation of that logic device is unstable. However, as described above, the phase of the horizontal synchronization signal is independent of the phase of the burst clock signal, so it cannot be guaranteed that the horizontal synchronization signal remains stable during the set-up and hold-times.
In cases when the horizontal synchronization signal is not stable during the set-up and hold-times, the logic gate or flip-flop may operate properly to detect the horizontal synchronization signal, or it may not. Thus, under this condition, there can be a one clock period uncertainty in the detection of the horizontal synchronization signal. Consequently, there can be a one clock period uncertainty in determining the first visible sample to be taken and stored. This means it is possible to process samples in successive frames which are spatially displaced one pixel in the raster, which seriously degrades the accuracy of such processing.
FIG. 2 illustrates one combination of burst locked clock and horizontal synchronization signal timing which may result in the uncertainty described above. In FIG. 2, the leading edge 301 of the horizontal synchronization signal, H SYNC, occurs just after a leading edge of cycle 0 of the burst locked clock, CLOCK. The horizontal synchronization signal, H SYNC, should be detected at clock cycle 1 of the leading edge of the burst locked, which is the next clock cycle following the leading edge 301 of the horizontal synchronization component H SYNC, as illustrated by rising edge 302 of the SYNC DETECTED signal. In turn, the sample clock should not begin until four clock cycles after that, or clock pulse 5, as shown in the fourth waveform, SAMPLE(RIGHT).
However, in this case, the horizontal synchronization signal H SYNC is not stable during the hold time of the flip flop at clock pulse 0. Thus, the flip flop may produce either a `high` or `low` signal at its output terminal, SYNC DETECTED, in response to cycle 0 of the burst locked clock, CLOCK. This is illustrated in FIG. 2 by the series of diagonal lines at the leading edge of the SYNC DETECTED signal. If the flip flop erroneously produces a `high` signal at the SYNC DETECTED output terminal in response to clock pulse 0, generating leading edge 303, then the sample clock SAMPLE will erroneously begin four cycles later at burst locked clock cycle 4. This is illustrated in FIG. 2 on the fifth waveform SAMPLE(WRONG).
FIG. 3 illustrates another combination of burst locked clock and horizontal synchronization signal timing which may result in the uncertainty described above. In FIG. 3, the leading edge 401 of the horizontal synchronization signal, H SYNC, occurs just before the leading edge of cycle 1 of the burst clock, CLOCK. In this case, as well, the horizontal synchronization signal H SYNC should be detected by clock pulse 1, as illustrated by rising edge 402 of the SYNC DETECTED signal. In turn, the sample clock should begin four clock cycles after that, or clock pulse 5, as shown in the fifth waveform, SAMPLE(RIGHT).
However, in this case, the horizontal synchronization signal H SYNC is not stable during the setup time of the flip flop at clock pulse 1. Thus, the flip flop may produce either a `high` or `low` signal at its output terminal, SYNC DETECTED, in response to cycle 1 of the burst locked clock CLOCK. This is illustrated in FIG. 3 by the series of diagonal lines at the leading edge of the SYNC DETECTED signal. If the flip flop does not produce a `high` signal at the SYNC DETECTED output terminal in response to cycle 1 of the burst locked clock CLOCK, generating leading edge 402, then the horizontal synchronizing signal H SYNC will not be detected until cycle 2 of the burst locked clock, CLOCK, as illustrated by leading edge 403 of the SYNC DETECTED signal. In this case, the sample clock SAMPLE will erroneously begin four cycles later at burst locked clock CLOCK cycle 6. This is illustrated in FIG. 3 on the fourth waveform SAMPLE(WRONG).
It is desirable that the location of the horizontal synchronization signal be accurately detected so that the spatial locations of the samples taken in relation to that signal can be located accurately. In this manner the frame processing will process corresponding samples and maintain the required accuracy of processing.